The 74F74 is a double favorable edge-triggered D -type flip -flop containing individual information, clock, set, and reset inputs; also true and complementary outputs. Establish (SD) and reset (RD) are asynchronous active low inputs and function independently of the clock input. After set and reset are inactive (high), data at the D input signal is transferred to the Q and Q outputs on the low -to -high transition of the clock. Data needs to be stable only 1 setup time before this low -to -high transition of the clock to get predictable performance. Clock triggering occurs at a voltage level and isn 't directly linked to the transition period of this positive -going pulse. Observing the hold period, data at the D input could be changed without affecting the degree of the output.