These devices contain two separate D-type positive-edge-triggered flip-flops. A low level at the clear inputs sets or resets the outputs whatever the amounts of their other inputs. Clock triggering occurs at a voltage level and isn 't directly associated with the rise time of this clock pulse. Observing the hold time interval, data at the D input signal could be changed without affecting the levels at the outputs.
The SN74LS74 IC is characterized for operation into 70 ºC from 0 ºC.